Conventional computer hardware components cannot function within both the work station markets, as well as the server computer markets. Peripheral components which interface with a designed hardware component vary depending on whether the hardware component is functioning within a work station environment or a server environment. Depending on the type of peripheral component, input/output (I/O) communication with the various peripheral components requires the ability to communicate with various interface protocols.
Within server platforms, peripheral component interfaces (PCI) devices, parallel port devices or integrated drive electronics (IDE) components are vital component, whereas in the work station platform, connections to various graphics devices via graphics cards and graphics ports such as, for example, accelerated graphics ports (AGP), is desired by consumers. Hence, designing of a memory controller hub that can function in both work station platforms as well as server platforms would simply require a memory controller hub capable of supporting interface protocols including both AGP protocols as well as interface protocols, such an a parallel-terminated, source-synchronous interface protocol. Unfortunately, the design of a hardware component which is capable of interfacing with various peripheral components and support the various (input/output) I/O protocols which run the peripheral components is complicated by the various types of signaling protocols implemented by the various I/O protocols.
The various I/O protocols which are supported may be either common-clock protocols or source-synchronous protocols. As known to those skilled in the art, source-synchronous I/O protocols refer to protocols wherein the data and the timing information are transported as a group. Also, depending on the protocol, the signaling may be series terminated or parallel terminated. For source-synchronous protocols, the strobe signals can be complimentary, negative edge driven, rising edge driven or single strobe. In addition, the I/O protocol may require transmission at N-times a core clock frequency.